Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs often include flash memory cells.
Generally, a transistor is covered by a high temperature oxide (HTO) and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlevel dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes must scale the dimensions of the transistors. That is, there must be proportional operational characteristics of structural elements in the ultra-small dimensions of a sophisticated transistor.
One problem associated with CMOS scaling involves forming of smaller and smaller apertures or spaces used in a variety of ways during the IC fabrication process. One way to shrink the critical dimension of “space” features, such as holes and trenches, is with the formation of spacers. However, the high temperature deposition process involved in conventional spacer formation requires additional etch and deposition steps.
In a conventional process, patterned photoresist is located above a spacer template of, for example, SiO2 that is above a polysilicon substrate. The spacer template is etched, the photoresist is removed, and spacer film is deposited. The spacer structures are formed from the spacer film and serve to shrink the aperture size associated with the spacer template. The substrate is etched using the spacer structures in the patterning. The spacers and spacer template are removed after the trench in the substrate is formed.
There is a need for a simplified spacer process for reducing critical dimensions. Further, there is a need to deposit carbon and form spacers directly on the photoresist pattern. Yet further, there is a need to reduce critical dimensions in integrated circuit fabrication using low temperature amorphous carbon spacers.